FIG. 1 is a block diagram of a prior art semiconductor ATE platform 10 architecture. Automatic test equipment platforms 10 (“ATE platforms,” “ATE testers,” or “testers”) are used to test electronic circuit devices (e.g., semiconductor components) during the manufacturing process. A device that is being tested is referred to as a “device under test” (“DUT”) 12 or, in the plural, as “devices under test” (“DUTs”) 12.
ATE tester 10 architecture includes, among other things, a user computer (“platform computer”) 14, one or more test instrument boards 16 (sometimes referred to as “test instruments,” for short), a device interface board (“DIB”) 18, and a device for moving devices under test 12 to and from the DIB 18, such as a handler or a prober 20. Hereinafter, the term handler/prober 20 will be considered implicitly inclusive of all devices that may be used to move DUTs 12 to and/or from the DIB 18. The platform computer 14 can be a personal computer (“PC”) or a workstation. The user interface software and the software that controls the handler/prober 20 for moving the DUTs 12 resides within the platform computer 14.
The DIB 18 is the component of the tester 10 that immediately connects to or contacts the signal receiving and signal outputting elements (“pins”) of the DUTs 12. The handler/prober 20 moves the DUTs 12 to the DIB 18 for testing, and off the DIB 18 once testing has concluded. In testers similar to tester 10 that test packaged semiconductor chips, the handler/prober 20 that moves the DUTs 12 to and from the DIB 18 may be referred to simply as a handler, while in testers similar to tester 10 that test pre-packaged semiconductor wafers, the handler/prober 20 that moves the DUTs 12 to and from the DIB 18 may be referred to simply as a prober.
Test instrument boards 16 communicate with the platform computer 14 via a communication board 22, and generate actual test signals that are applied to the pins of the DUTs 12 via the DIB 18, and/or capture the signals returned (“return signals”) by the DUTs 12 via the DIB 18. Most testers 10 have dozens of test instrument boards 16. Test instrument boards 16 may contain a test vector sequencer and a DIB interface through which they communicate with the DIB 18. A backplane could be used instead of or in addition to the communication board and some in the industry may consider the backplane to be equivalent to the communication board in some respects.
The test vector sequencer is the component of the test instrument boards 16 that controls the timing of the application of test signals to the DUTs 12, and the capture of return signals from the DUTs 12. A signal applied to one input pin of the DUTs 12 or captured from one output pin of the DUTs 12 is referred to as a “vector.” A signal applied to an input pin of the DUTs 12 to test that each of the DUTs 12 operates correctly is hence referred to as a “test vector.”
DUTs 12 generally possess multiple input and output pins and some pins can serve both for input and output purposes. DUTs 12 may possess significant internal complexity, such as multiple test vectors that must be applied to multiple input pins in a specific pre-determined sequence to properly test a characteristic, feature, or function, of the DUTs 12. A collection of test vectors for such a test comprises a “test pattern.”
Test engineers may write such test patterns using programming languages such as C, VHDL, or Verilog, in accordance with the design and specification of the DUTs 12. Test patterns in programming language form are then compiled into machine-readable binary code test patterns. A test pattern compiler 26, a component of the software that runs on the platform computer 14, performs the compilation. The compiled machine-readable binary code test pattern may then be loaded from the platform computer 14 to each of the test instrument boards 16 before the ATE platform 10 starts the testing of the DUTs 12.
Similarly, once the test has concluded, the collection of vectors captured from the output pins of the DUTs 12 may be transferred from the test instrument boards 16 that captured those vectors to the platform computer 14 for the purposes of test result analysis. When testing DUTs 12 in the context of a manufacturing operation, one priority may be to complete testing of the devices as quickly as possible. Long test times reduce the throughput of the manufacturing process, effectively increasing production costs of each device.
FIG. 2 is the flow chart of a prior art semiconductor device test 70 performed by using the ATE platform 10 shown in FIG. 1. As shown, a test is written in a programming language (block 72). The test is compiled into binary code test patterns using the test pattern compiler 26 on the platform computer 14 (block 74). The binary code test pattern is transferred through the communication board 22 to the test instrument boards 16 (block 76). The handler/prober 20, at the direction of the platform computer 14, puts DUTs 12 on the DIB 18 (block 78). The test pattern is applied through the DIB interface to the DUTs 12 on the DIB 18 (block 80). Test vectors are captured by the test instrument boards 16 and transferred back to the platform computer 14 (block 82). Analysis of the test vectors may then be performed at the platform computer 14 (block 84). The platform computer 14 then causes the handler/prober 20 to remove the tested DUTs 12 from the DIB 18 and sort it according to the analysis results (block 86).
It is not unusual for a plurality of test instrument boards 16 to be utilized in testing one of the DUTs 12. For instance, an ATE tester 10 testing a 50-pin DUT 12 may utilize 5 or more test instrument boards 16, operating concurrently. That ATE tester 10 may be testing a handful of 50-pin DUTs 12 concurrently, utilizing 25 or more test instrument boards 16. However, the more test instrument boards 16 that are used concurrently, the more difficulty the platform computer 14 has compiling test results and the more the communication board 22 may operate to bottleneck the signals transmitted between the various test instrument boards 16 and the platform computer. The architecture for this type of ATE tester 10 is shown in FIG. 3.
ATE tester 10 architecture may rely on a single, stand-alone ATE tester 10, having one platform computer 14 and one or more test instrument boards 16, to perform tests on one DUT 12 or multiple DUTs 12 simultaneously. FIG. 3 is a block diagram of a prior art semiconductor ATE platform 10 architecture utilizing a plurality of test instrument boards 16. Most marketable ATE testers 10 utilize 16-64 test instrument boards. In cases where multiple DUTs 12 are tested in parallel, an ATE tester 10 may include multiple test instrument boards 16, all connected to the single platform computer 14, with different subsets of the test instrument boards 16 dedicated to each DUTs 12 being tested. However, the large number of vectors in some test patterns, the large number of vectors returned by some tests, the large number of tests that can be required to test DUTs 12 satisfactorily, the need to communicate test patterns and captured output vectors to and from the platform computer 14 and test instrument boards 16, and inherent bandwidth limitation of a communications board 22 and connection between the platform computer 14 and the test instrument boards 16 impose a limit on the number of DUTs 12 that can be simultaneously tested by a stand-alone ATE tester 10 operated by one test engineer (“user”). Operation of the ATE tester 10 would be more efficient and the bandwidth limitations obviated by limiting the number of test instrument boards 16, but limiting the number of test instrument boards 16 directly limits how quickly the ATE tester 10 can functionally test the DUTs 12.
For example, some companies utilize an ATE tester 10 having one platform computer 14 with an 800 Mbps firewire connection to the communications board 22. About 60-70 test instrument boards 16 are attached to the communications board 22. As a result, if one of the test instrument boards 16 communicates to the platform computer 14 through the communications board 22 and firewire, it can communicate at a rate of up to 800 Mbps under ideal conditions. In general, under optimal conditions, only 70-90% efficiency can be achieved because of the physical impedance on the communication board 22 and firewire. However, if 60-70 test instrument boards 16 are trying to connect to the platform computer 14 at the same time, efficiency is dramatically reduced, and the platform computer 14 must do time-division multiplexing communication. Further, it is not unusual for many test instrument boards 16 to need to connect to the platform computer 14 at the same time, making inefficiency in the system common.
FIG. 4 is a block diagram of a prior art ATE system 110, in accordance with an invention disclosed in US Patent Application Publication Number 2003/0062888 to Magliocco, et al. The ATE system 110 includes a system controller 128. A plurality of testers is in communication with the system controller 128. Each tester is contained within an enclosure 150A-N and includes a platform computer 114A-N. Each of the platform computers 114A-N is in communication with a plurality of test instrument boards 116A-N contained within the enclosure 150A-N of the tester. At least one device interface board 118A-N is provided for each tester, although Magliocco, et al. discloses a collective device interface board 118X that is connectable to the plurality of device interface boards 118A-N. Each of the plurality of test instrument boards 116A-N is in communication with at least one device interface board 118A-N mounted on the enclosure 150A-N of its respective tester.
As disclosed by Magliocco, et al., this prior art ATE system 110 is directed toward scaleable testers. Independently operable testers can be interconnected through their enclosures 150A-N allowing them to “enable testing of a DUT having a number of pins greater than can be accommodated on any single tester, or to simultaneously test a large number of smaller DUTs in parallel on different testers.” Paragraph 8 of Magliocco, et al. Unfortunately, a plurality of inefficient testers stacked together, while capable of testing a greater quantity of pins concurrently, have the same inefficiency as unstacked testers.
Thus, a heretofore unaddressed need exists in the industry to overcome the aforementioned deficiencies and inadequacies.